In a typical voltage converter, the output voltage is regulated by monitoring a level of the output voltage, comparing that monitored level to a predetermined desired level and developing a response to that comparison to minimize the difference between the monitored level and the predetermined desired level of the output voltage. FIG. 1 illustrates a typical buck converter circuit for providing a regulated output voltage. Referring to FIG. 1, a supply voltage node Vs is coupled to a first terminal of a switch S1. A second terminal of the switch S1 is coupled to a first terminal of a switch S2 and to a first terminal of an inductor L1. A second terminal of the inductor L1 is coupled to a first terminal of a capacitor C1, forming an output node Vo, and to a first terminal of a resistor R1. A second terminal of the switch S2 and a second terminal of the capacitor C1 are coupled to a ground node. A load RL can be coupled across the capacitor C1.
A second terminal of the resistor R1 is coupled to a first terminal of a resistor R2 and to an inverting input of an amplifier U1. A second terminal of the resistor R2 is coupled to the ground node. A reference voltage VREF1 is coupled to a non-inverting input of the amplifier U1. An output of the amplifier U1 forms an error signal VEAO1 which is coupled to a non-inverting input of a comparator U2. An oscillator U3 generates a periodic ramp signal VRAMP1 having a fixed frequency which is coupled to an inverting input of the comparator U2. An output of the comparator U2 forms a signal VSC1 which is coupled to control the switch S1. The signal VSC1 is inverted by an inverter U4 for controlling the switch S2.
FIG. 2 illustrates a timing diagram for the signal VRAMP1 and the signal VEAO1. FIG. 3 illustrates a timing diagram for the signal VSC1. Referring to FIGS. 1-3, when the signal VSC1 is logical high voltage, the switch S1 is closed and the switch S2 is open. When the switches S1 and S2 are in this condition, a current from the supply node Vs charges the inductor L1 with energy. When the signal VSC1 is a logical low voltage, the switch S1 is open and the switch S2 is closed. Therefore, energy stored in the inductor L1 is transferred to the capacitor C1. By alternately closing and opening the switches S1 and S2 in this manner, an output voltage can be formed across the capacitor C1 which can be applied to the load RL. The amount of energy stored in the inductor L1 and transferred to the capacitor C1 can be controlled by adjusting the time period during which the switch S1 is closed.
A resistive divider comprising the resistors R1 and R2 forms a voltage that is proportional to the output voltage across the capacitor C1. A difference between the reference voltage VREF1 and the voltage formed by the resistive divider is amplified by the amplifier U1, forming the error signal VEAO1. The error signal VEAO1 is compared to the ramp signal VRAMP1 by the comparator U2, forming the signal VSC1. Accordingly, if the voltage across the capacitor C1 increases, the signal VEAO1 decreases. This reduces the duty cycle of the signal S1 such that the amount of energy transferred to the capacitor C1 is reduced, thereby reducing the voltage across the capacitor C1. If the voltage across the capacitor C1 decreases, the signal VEAO1 increases. This increases the duty cycle of the signal S1 such that the amount of energy transferred to the capacitor C1 is increased, thereby increasing the voltage across the capacitor C1. Therefore, the output voltage at the node Vo is regulated in a feedback loop to remain at a constant level. Because the circuit illustrated in FIG. 1 utilizes the topology of a buck converter, the output voltage Vo cannot be higher than the input voltage Vs.
Because the duty cycle of the signal VSC1 is controlled by monitoring the output voltage, a feedback path, such as through the resistive divider, is required to be coupled to the output node Vo. When such a circuit is implemented in an integrated circuit, this feedback path requires a dedicated pin of the integrated circuit package. The size and cost of an integrated circuit, however, increases as the number of pins increases. Further, the inductor L1 and capacitor C1 in the feedback loop can contribute to instability of the feedback loop. Additional components can be required to counteract this effect. It is therefore desired to provide a regulated output voltage without requiring a feedback path coupled to the output node Vo.
A boost converter having a prior art feedback loop for monitoring the output voltage is illustrated in FIG. 4. A supply node Vs2 is coupled to a first terminal of an inductor L2. A second terminal of the inductor L2 is coupled to a first terminal of a switch S3 and to a first terminal of a switch S4. A second terminal of the switch S3 is coupled to the ground node. A second terminal of the switch S4 is coupled to a first terminal of a capacitor C2 and to a first terminal of a resistive divider comprising resistors R3 and R4. A second terminal of the capacitor C2 and a second terminal of the resistive divider are coupled to the ground node.
An output voltage Vo2 is formed across the capacitor C2 by appropriately opening and closing the switches S3 and S4. When the switch S3 is closed and the switch S4 is open, the input voltage Vs2 charges the inductor L2 with a current. When the switch S3 is open and the switch S4 is closed, the inductor L2 discharges energy into the capacitor C2. A load RL2 is coupled across the capacitor C2 to receive the output voltage Vo2.
A voltage formed by the resistive divider is utilized as an input to a control circuit for controlling the duty cycle of the switches S3 and S4 to regulate the output voltage Vo2. An amplifier U5 forms an error signal VEAO2 that is representative of a difference between the output voltage Vo2 and a desired output voltage, represented by VREF2. A comparator U6 compares the error signal VEAO2 to a periodic ramp signal VRAMP2. An output of the comparator U6 forms a signal VSC2 which is coupled to control the switch S3. The signal VSC2 is inverted by an inverter U8 for controlling the switch S4.
If the error signal VEAO2 increases, the period of time during which the switch S3 is closed and the switch S4 is open is increased to charge the inductor L2 with more energy which is then discharged into the capacitor C2 when the switch S3 is opened and the switch S4 is closed. If the error signal VEAO2 decreases, the period of time during which the switch S3 is closed and the switch S4 is open is decreased. Therefore, the output voltage is regulated in a feedback loop. Because the circuit illustrated in FIG. 4 utilizes the topology of a boost converter, the output voltage Vo2 can be higher than the input voltage Vs2.
Because the duty cycle of the switches in the buck converter illustrated in FIG. 1 and in the boost converter illustrated in FIG. 4 are controlled by monitoring the output voltage Vo, a feedback path, such as through the resistive divider, is required to be coupled to the output node. When a circuit for controlling such a buck or boost voltage converter is implemented in an integrated circuit package, this feedback path requires a dedicated pin of the integrated circuit package. The size and cost of an integrated circuit, however, increases as the number of pins increases. It is desired, therefore, for a circuit for controlling a buck or boost converter to provide a regulated output voltage without the need for a feedback path for monitoring the output voltage.